Content of the lecture:
I. Basics of digital circuit technology and design:
- MOS Transistor as a switch: CMOS Inverter, Transmission Gate
- Combinational logic structures and gates: basic gates and combinational logic gates,
- Sequential logic gates, Logic family NMOS, CMOS static, CMOS dynamic, Layout
- Basic characteristics of gates:
- Delays, power dissipation, noise margin, hazards
- Sequential circuit elements: latch, flip-flop, memory cell, Schmitt trigger,
- Oscillator, timing
- IC design strategies: Full Custom, Standard cells, Gate Arrays, FPGA
II. Basics of sequential circuits:
- Classification of sequential circuits : synchronous, mesosynchronous, plesiosynchronous, asynchronous
- Synchronous circuits 1: one phase signal, timing, skew, fade, pipelining, asynchronous reset
- Synchronous circuits 2: two phase signals, timing, fade, slack-Passing
III. Digital Memory:
- Read-Write-Memory: static RAM, dynamic RAM, multi-port RAM, layout
- Read-Only-Memory: masc programmable ROM (NAND, NOR), layout
- Programmable ROM: EEPROM, FLASH
IV. Elements of Register Transfer Designs:
- Digital Arithmetic: Adder, Subtractor, Multiplier, Divider, ALUs
- Elements of data paths: Multiplexer, Shifter, Counter (binary, Gray, Johnson), Decoder
- Control of data paths: state machine, Hot-One-Coding, counter based FSM, Microprocessor
IV. Field-programmable gate array (FPGA):
- Programmable ASIC Design
- CPLD and FPGA Architectures
- FPGA Logic Cells and Architecture
- FPGA Programmable Interconnect and I/O Cells
- FPGA Implementation of Combinational Logic
- FPGA Implementation of Sequential Logic
- Timing Issues in FPGA Synchronous Circuit Design
- Arithmetic Circuit Implementation
- FPGAs in DSP Applications
- FPGA Microprocessor
- Design Example 1: A Simple SDRAM Tester
- FPGA Implementation of Universal Asynchronous Receiver and Transmitter (UART)
- FPGA In-System Configuration
Termine:
| Vorlesung: |
Mittwochs, 14:00 bis 15:30, BA 143 |
| Übung: | Mittwochs, 15:45 bis 16:30, BA 143 |
- Lehrende(r): Belmin Alic